The invention relates to a method of manufacturing an analog circuit integrated with an I.sup.2 L circuit on a common semiconductor chip of the P-conductive type in the course of common technological process steps with vertical NPN switching transistors in the I.sup.2 L circuit and with linear vertical NPN transistors in the analog circuit.
The manufacture of I.sup.2 L circuits and bipolar analog circuits on a common semiconductor chip of the type mentioned above is known for example from the Valvo Reports, Volume XVIII, Book 1/2, pages 215-226. In the integrated injection logic circuit (I.sup.2 L) lateral PNP transistors, also called injectors, are used as current sources for vertical NPN switching transistors. An I.sup.2 L-logic element works with very small power consumption and needs little crystal surface so that high packing densities can be achieved.
Bipolar analog circuits contain a vertical NPN transistor which is operated, however, in contrast to the NPN switching transistor of the I.sup.2 L circuit, in the reverse direction. Thus generally with an I.sup.2 L circuit built up on a P-substrate, N.sup.+ regions diffused in the P-region, serving as the base, are used as collectors and the corresponding N.sup.+ regions of bipolar analog circuit are used as emitters.
When combining circuits on a common semiconductor chip both circuits can be manufactured in a common process. Only one further step is needed for manufacturing deep N.sup.+ regions for decoupling of adjacent I.sup.2 L gates.
In I.sup.2 L logic circuits, the binary potential conditions are below 1 V. The maximum collector voltage of their NPN switching transistors is approximately 2 to 5 V caused by a desired high operating frequency and an upward current amplification factor of approximately 4. However, in order to apply a fairly high switching power for analog circuits, supply voltages of about 30 V and more are often necessary. For this, it is known to apply epitaxial layers having a high specific resistance (1 to 3 .OMEGA. cm) and large thicknesses (10 to 15 .mu.m) on to the substrate. However, the current amplification of the upwardly operated NPN switching transistors required for I.sup.2 L circuits cannot be carried out without problems.